1. Field of the Invention
The present invention relates to a memory controller which can have memory access, a data processor which has the memory controller and a central processing unit, and a data processing system which has the data processor and a memory. The invention also relates to a technique which is useful when applied to a semiconductor device having the above-mentioned items formed in one package.
2. Description of the Prior Art
A data processor having a central processing unit (CPU) makes access to memories which include a main memory and a cache memory. The main memory stores programs to be run and data to be processed by the CPU. The main memory formed in a semiconductor device is known to be a large-capacity memory which is typically made of volatile memories such as a DRAM (dynamic random access memory) or nonvolatile memories such as a flash memory. The cache memory is made of memories having relatively small capacities such as a SRAM (static random access memory). The cache memory is located between the CPU having a high-speed operation and the main memory which operates slower than the CPU, thereby absorbing difference in their operational speeds.
For a high-speed operation of a data processing system having a CPU, cache memory and main memory, there has been a technique of using the sense amplifiers of the DRAM of main memory in a manner like cache memory. The technique of using DRAM""s sense amplifiers in a manner like cache memory will be explained as follows. The data processor first puts out a row address to the DRAM. The DRAM has its word lines selected by a row address, and data of the full one line on the selected word line are transferred to and held by the sense amplifiers. The data processor next puts out a column address to the DRAM. The column address selects certain column switches, causing the sense amplifiers to release the data.
The sense amplifiers hold the data of the full one line of the selected word line continuously after the readout of data. At the next DRAM access by the data processor, if the row address is the same as the previous one, the data processor puts out only a column address. Generally, word line selection takes a relatively long time, whereas by retaining data in the sense amplifiers, it is possible to read out data in a short time for an event of access with the same word line, i.e., access to the same page.
However, the foregoing prior art involves the following problem. In case data is to be read out from a word line which is different from the word line where data are held by sense amplifiers, i.e., at the occurrence of cache error in the cache-wise use of sense amplifiers, it is necessary to cancel the selection of the immediate word line, precharge the data lines, and thereafter select a new word line. The need of precharging at this access results in a longer data read time than usual data readout.
There are several techniques intended to overcome the above-mentioned problem as described in JP-A Nos. 1994-131867, 1995-78106 and 2000-21160.
The JP-A No. 1994-131867 discloses a technique for speeding up the read and write operations of a DRAM, with its sense amplifiers being used as cache memory, even at the occurrence of cache error. Specifically, the DRAM has its data lines divided into data lines which are connected to the memory cells and pre-amplifiers, and global data lines which are connected to the main amplifiers used as cache memory.
It also shows the arrangement of a means of shorting the data lines, which are connected with the memory cells and pre-amplifiers, independently of the global bit lines. This arrangement enables the precharging of the data lines which are connected with memory cells and pre-amplifiers even in the data holding state for one page of the main amplifiers connected to the global data lines, and thus enables the preparation for reading out data from another page, i.e., another word line.
The JP-A No. 1995-78106 discloses a technique for speeding up the read and write operations of a DRAM, with its sense amplifiers for memory banks being used as cache memory, even at the occurrence of alternate access between memory banks. Specifically, a data processing system is provided in its DRAM control circuit with row address memory means in correspondence to the memory banks. This arrangement enables the judgement as to whether the memory access is to the same row address as the previous access, i.e., whether the access is to the same page, for each memory bank, and thus enables the high-speed block data transfer.
The JP-A No. 2000-21160 discloses a technique for the use of sense amplifiers for memory banks of a multi-bank DRAM as cache memory. It shows, with the intention of enhancing the hit rate of sense amplifier cache, a means of advanced reading of data of a predicted address based on the advanced issuance of the next address which is determined by adding a certain offset value to the previous address of the memory bank which has been accessed previously.
The inventors of the present invention have found the unevenness of access to the main memory in reading a program to be run by the central processing unit or reading data out of the main memory. For example, there are a case of frequent access to the same page (same word line) of the main memory, a case of frequent access to different pages, and a case of access to a same page and access to different pages at an equal frequency. The unevenness of access results largely from the characteristic of a program. The inventors of the present invention have found that the above-mentioned prior arts cannot deal with the unevenness of access frequency sufficiently and cannot solve the problem of slower data read/write operations from/to the main memory due to the unevenness.
An object of the present invention is to provide a data processor having its main memory sense amplifiers, e.g., DRAM, used as cache memory, and a data processing system having the data processor and main memory, with the intention being the speed-up of main memory access thereby to speed up the whole data processing system.
These and other objects and novel features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
Representing means of carrying out the present invention are as follows.
There is provided a means of checking as to whether the immediate memory access is to the same page as of the previous access or to a different page, and switching the memory control mode accordingly. There is provided a memory controller having a page mode, wherein the page mode is cancelled at an event of different page access or the row address output is skipped at an event of same page access. Upon canceling the page mode, it enters the operation mode of precharge control after putting out a column address at an event of memory access.
The precharge control is to bring the RAS signal to the high level on expiration of a certain time length following the output of a column address. In other words, the precharge control is to issue a precharge command on expiration of a certain time length following the output of the column address.
The memory controller may have a register for setting as to whether or not the cancellation of page mode is to take place. The page mode will also be called xe2x80x9cpage-on modexe2x80x9d or xe2x80x9cRAS-down modexe2x80x9d.
Another means is a memory controller having a page mode, wherein the page mode is cancelled at successive events of access to different pages. At an event of different page access, it implements precharge control and thereafter puts out a row address, or it implements the precharge control without the row address output at an event of same page access.
The precharge control is to put out a high-level RAS signal. In addition, the precharge control is to issue a precharge command, and put out a row address on expiration of a certain time length following the issuance of the precharge command.
Upon canceling the page mode, the memory controller enters the operation mode of bringing the RAS signal to the high level on expiration of a certain time length following the column address output at an event of memory access. In addition, upon canceling the page mode, it enters the operation mode of issuing the precharge command on expiration of a certain time length following the column address output at an event of memory access.
The memory controller may have a register for setting as to whether or not the cancellation of page mode is to take place.
Another means is a memory controller having a first operation mode and second operation mode, and it switches from the first mode to the second mode at an event of access to a second page which is different from a first page, following the access to the first page. In the second mode, it switches from the second mode to the first mode at an event of access to a third page following the access to the third page. The first mode is to have successive events of access to a same page, and the second mode is to have successive events of access to different pages. The time expended to make access to a same page a certain number of times in the first mode is shorter than the time expended to make access to the same page the same number of times in the second mode.
Another means is a memory controller having a first operation mode in which memory access takes place with the output of a column address and without the output of a row address, and a second operation mode in which memory access takes place with the implementation of precharge control following the output of a row address and column address. It switches to the first mode at an event of memory access with the output of a row address and column address following the implementation of precharge control. At an event of memory access to a same row address in the second mode, it switches to the first mode.
The memory controller may have a register for setting as to whether or not the switching between the first and second modes is to take place.
The precharge control of the second mode is to put out a high-level RAS signal on expiration of a prescribed time length following the column address output. In addition, the precharge control of the second mode is to issue the precharge command on expiration of a prescribed time length following the column address output.
Another means is a data processing system including a central processing unit (CPU) which puts out an address, a memory controller which is supplied with the address and adapted to operate in a first mode and second mode, and a memory which is controlled by the memory controller. In the first mode, the memory controller switches from the first mode to the second mode at an event of access to a second page which is different form a first page following the access to the first page.
The data processing system has a register circuit for setting as to whether or not the switching between the first and second modes is to take place. The CPU can alter the setting of the register circuit. The CPU and memory controller may be formed on a same semiconductor chip. Alternatively, the CPU, memory controller memory may be formed in one semiconductor package.
Another means is a memory controller having a first memory access mode in which it makes access to the memory by putting out a column address but without putting out a row address, a second memory access mode in which it precharges the memory and thereafter puts out a row address and column address, and a third memory access mode in which it puts out a row address and column address to the memory and thereafter precharges the memory, and operating to have the first memory access, and thereafter the second memory access, and thereafter the third memory access. Alternatively, the first memory access may be followed by the second memory access a number of times, which may be followed by the third memory access.
Still another means is a memory controller having an input node, a first register circuit which holds the address put to the input node, a first comparator circuit which compares the address put to the input node with the address held by the first register circuit, a second comparator circuit which compares the output of the first comparator circuit with the contents of a second register circuit, and a first circuit which is set to a first state or second state depending on the output of the second comparator circuit. The first comparator circuit releases a value which is the number of times of the comparison result of inequality or disagreement between the address held by the first register circuit and the address put to the input node, and the second comparator circuit compares the count value provided by the first comparator circuit with the contents of the second register circuit.
The memory controller may further include a second circuit which releases a first and second parts of the address put to the input node in response to the setting of the first state of the first circuit or the first part of the address put to the input node in response to the setting of the second state of the first circuit, and an output node which releases the output of the second circuit to the memory.
Alternatively, the first register circuit holds part of the address put to the input node, and the first comparator circuit compares part of the address put to the input node with part of address held by the first register circuit. Alternatively, the first comparator circuit compares a first address put to the input node with a second address which has been put to the input node before the first address.
Alternatively, an address put to the input node has a number of bits and the first register circuit has a number of fields, and the first comparator circuit compares the first address with the address which is held in one of the fields specified by a certain bit of the first address. The first and second parts of address may be a row address and a column address, respectively, of the memory. The input node may be supplied with an address which is put out by the CPU.
Another means is a memory controller which can adjust the correspondence between an address put out by the CPU and a memory address based on information of the line size, index and tag indicative of the structure of the primary cache of CPU and information of the column address, row address and bank address indicative of the structure of the memory accessed by the CPU.
In combination with the foregoing means, with the intention of further raising the frequency of access to the same page of the memory, an event of access to a memory is followed by the advanced issuance of the next address (evaluated by the addition of a certain offset value to the previous address) and data of the predicted address is held in the sense amplifiers of a bank in a different memory.
The memory may be controlled based on the judgement as to whether the previous predicted address is to the same page as the immediate access, and the predicted address is validated in the case of a same page access or invalidated in the case of a different page access.
The memory controller may further include an additional arrangement for aligning automatically an address put out by the CPU and a memory address based on information of the line size, index and tag indicative of the structure of the primary cache of CPU and information of column address, row address and bank address indicative of the structure of the memory accessed by the CPU. This additional arrangement can be either added to the foregoing arrangement or used independently to achieve the effectiveness of the present invention.